Pin Assignment for Multi-FPGA Systems 1 (Extended Abstract)

There is currently great interest in using systems of FPGAs for logic emulators, custom computing devices, and software accelerators. An important step in making these technologies more generally useful is to develop completely automatic mapping tools from high-level specification to FPGA programming files. In this paper we examine one step in this automatic mapping process, the selection of FPGA pins to use for routing inter-FPGA signals. We present an algorithm that greatly increases mapping speed while also improving mapping quality.

[1]  Gaetano Borriello,et al.  Pin assignment for multi-FPGA systems , 1994, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines.

[2]  Martine D. F. Schlag,et al.  Architectural tradeoffs in field-programmable-device-based computing systems , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.

[3]  Pinaki Mazumder,et al.  VLSI cell placement techniques , 1991, CSUR.