Transactional Level Verification and Coverage Metrics by Means of Symbolic Simulation

Assuring correctness of digital designs is one of the major tasks in the system design flow. Formal methods have been proposed to accompany commonly used simulation approaches. The vital part missing in all these techniques is the so-called coverage of functionalities. This paper aims to tackle this problem by proposing a new method to verify the sequence of transactions among the modules of a system level design. To accomplish this, we propose a model that captures the transactions of a given high level design. By symbolically simulating this abstract model we can generate the set of all possible transaction sequences of the system design. Verification of properties is carried out on these transactions stepwise. According to the status of the verification results, every transaction will be assigned a special state which will be inherited by its succeeding transactions. Once reaching the end, we calculate the coverage of the design functionalities by the set of properties. This approach finds at least two interesting applications. First, it can guide the verification engineer during property specification by providing the set of abstract properties that cover the basic functionalities. Secondly, the generated transaction sequences can be exploited to emit monitors for simulation runs of transactional level SystemC designs.