Recent Advances in High Performance CMOS Transistors: From Planar to Non-Planar

41 More than 40 years later, Gordon’s Moore accurate observation1— that the number of transistors in an integrated circuit doubles roughly eighteen months—continues to be the guiding principle of the semiconductor industry. We have almost taken for granted the apparent corollary: as transistor count increases, each transistor becomes smaller, faster, and cheaper. Today, the transistor gate length (LG) in production is approximately 28 nanometers. Further geometric scaling of conventional silicon MOSFET devices faces many fundamental challenges, such as: excessive gate leakage current, exponentially increasing source to drain sub-threshold leakage current, gate stack reliability and channel mobility degradation from increasing electric field rising dynamic power dissipation (CV2f) from non-scaled supply voltages, bandto-band tunneling leakage at high body doping levels, device to device variation from random dopant fluctuation effects, and Recent Advances in High Performance CMOS Transistors: From Planar to Non-Planar