Crosstalk avoidance and error-correction coding for coupled RLC interconnects

On-chip interconnect delay and crosstalk noise have become an important factor for performance and signal integrity as a result of increase in device densities and operating clock frequency in deep sub-micrometer (DSM) VLSI circuits. With faster rise times and lower resistance, interconnects exhibit significant inductive effect compared to capacitive effect. Therefore, various existing coding techniques for capacitive crosstalk reduction in resistive-capacitance (RC) interconnects are not suitable for resistive-inductance-capacitance (RLC) interconnects in high-speed circuits. At the same time, on-chip interconnects are susceptible to various DSM noise sources. Error-correction coding (ECC) improves interconnect-reliability against DSM noise. This paper proposes a modified boundary shift coding technique that simultaneously addresses inductance-dominant cross-talk noise reduction and error-correction for coupled RLC interconnects. Results show that proposed coding achieves up to 50% reduction in additional wiring requirement.

[1]  Luca Benini,et al.  Low power error resilient encoding for on-chip data buses , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[2]  Naresh R. Shanbhag,et al.  Area and energy-efficient crosstalk avoidance codes for on-chip buses , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[3]  Yu Hu,et al.  Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[4]  Igor L. Markov,et al.  Error-correction and crosstalk avoidance in DSM busses , 2003, SLIP '03.

[5]  Cecilia Metra,et al.  Exploiting ECC redundancy to minimize crosstalk impact , 2005, IEEE Design & Test of Computers.

[6]  Naresh R. Shanbhag,et al.  Coding for systern-on-chip networks: a unified framework , 2004, Proceedings. 41st Design Automation Conference, 2004..

[7]  M.H. Chowdhury,et al.  Joint coding for RLC coupling-aware on-chip buses , 2008, 2008 51st Midwest Symposium on Circuits and Systems.

[8]  Krishna C. Saraswat,et al.  Effect of scaling of interconnections on the time delay of VLSI circuits , 1982 .

[9]  Kiyoung Choi,et al.  Partial bus-invert coding for power optimization of system level bus , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[10]  A. Deutsch,et al.  The importance of inductance and inductive coupling for on-chip wiring , 1997, Electrical Performance of Electronic Packaging.

[11]  Eby G. Friedman,et al.  Crosstalk modeling for coupled RLC interconnects with application to shield insertion , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Sung-Mo Kang,et al.  Coupling-driven signal encoding scheme for low-power interface design , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[13]  Keith A. Jenkins,et al.  When are transmission-line effects important for on-chip interconnections? , 1997 .

[14]  Mircea R. Stan,et al.  Bus-invert coding for low-power I/O , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[15]  Yao-Wen Chang,et al.  RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Denis Deschacht.  DSM interconnects: importance of inductance effects and corresponding range of length , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Naresh R. Shanbhag,et al.  Toward achieving energy efficiency in presence of deep submicron noise , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[18]  Uri C. Weiser,et al.  Interconnect-power dissipation in a microprocessor , 2004, SLIP '04.

[19]  S. Wicker.  Error Control Systems for Digital Communication and Storage , 1994 .

[20]  M. B. Srinivas,et al.  Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects , 2007, GLSVLSI '07.

[21]  Naresh R. Shanbhag,et al.  Coding for system-on-chip networks: a unified framework , 2005, IEEE Trans. Very Large Scale Integr. Syst..

[22]  Bashir M. Al-Hashimi,et al.  Minimization of crosstalk noise, delay and power using a modified bus invert technique , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[23]  K. Skadron,et al.  Odd/Even bus invert with two-phase transfer for buses with coupling , 2002, Proceedings of the International Symposium on Low Power Electronics and Design.

[24]  Anantha Chandrakasan,et al.  Bus energy minimization by transition pattern coding (TPC) in deep sub-micron technologies , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).