Challenges and emerging solutions in testing HBM IO & systems

With advances in VLSI technology, process, packaging and architecture, System on a Chip (SoC) continue to increase in complexity. This has resulted in an unprecedented increase in design errors, manufacturing flaws and customer returns in modern VLSI systems related to High Speed I/O circuits. The situation will be exacerbated in future systems with smaller form factors, higher integration complexity, Embedded I/O's, and more complex manufacturing process. Systems using High Bandwidth Memory (HBM) with embedded DRAM interconnected via a high density substrate with interposer-like technologies (2.5D packaging) are being introduced in a broad array of products. In this work we define a new testability methodology for 2.5D products. As opposed to conventional testing, 2.5D IC test flows are more complex and new DFT methodologies will be presented that provide good coverage and visibility to isolate failures in Production Manufacturing Tests.