Carbon nanotube circuits: Opportunities and challenges

Carbon Nanotube Field-Effect Transistors (CNFETs) are excellent candidates for building highly energy-efficient digital systems. However, imperfections inherent in carbon nanotubes (CNTs) pose significant hurdles to realizing practical CNFET circuits. In order to achieve CNFET VLSI systems in the presence of these inherent imperfections, careful orchestration of design and processing is required: from device processing and circuit integration, all the way to large-scale system design and optimization. In this paper, we summarize the key ideas that enabled the first experimental demonstration of CNFET arithmetic and storage elements. We also present an overview of a probabilistic framework to analyze the impact of various CNFET circuit design techniques and CNT processing options on system-level energy and delay metrics. We demonstrate how this framework can be used to improve the energy-delay-product (EDP) of CNFET-based digital systems.

[1]  W. Haensch,et al.  Scalable and fully self-aligned n-type carbon nanotube transistors with gate-all-around , 2012, 2012 International Electron Devices Meeting.

[2]  Robert F. Pierret,et al.  Semiconductor device fundamentals , 1996 .

[3]  Christoforos E. Kozyrakis,et al.  JouleSort: a balanced energy-efficiency benchmark , 2007, SIGMOD '07.

[4]  Hai Wei,et al.  Monolithic three-dimensional integrated circuits using carbon nanotube FETs and interconnects , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[5]  W. Haensch,et al.  High-density integration of carbon nanotubes via chemical self-assembly. , 2012, Nature nanotechnology.

[6]  Georges G. E. Gielen,et al.  Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[7]  S. Wind,et al.  Carbon nanotube electronics , 2003, Digest. International Electron Devices Meeting,.

[8]  J. Rogers,et al.  High-performance electronics using dense, perfectly aligned arrays of single-walled carbon nanotubes. , 2007, Nature nanotechnology.

[9]  H.-S. Philip Wong,et al.  Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[10]  H. Dai,et al.  Preferential Growth of Semiconducting Single-Walled Carbon Nanotubes by a Plasma Enhanced CVD Method , 2004 .

[11]  Giovanni De Micheli,et al.  Carbon nanotube correlation: Promising opportunity for CNFET circuit yield enhancement , 2010, Design Automation Conference.

[12]  James Laudon,et al.  Performance/Watt: the new server focus , 2005, CARN.

[13]  A. Rinzler,et al.  An Integrated Logic Circuit Assembled on a Single Carbon Nanotube , 2006, Science.

[14]  H.-S. Philip Wong,et al.  Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  H.-S. Philip Wong,et al.  Performance benchmarks for Si, III–V, TFET, and carbon nanotube FET - re-thinking the technology assessment methodology for complementary logic applications , 2010, 2010 International Electron Devices Meeting.

[16]  T Mizutani,et al.  Change in carrier type in high-k gate carbon nanotube field-effect transistors by interface fixed charges , 2010, Nanotechnology.

[17]  J. Rogers,et al.  Improved Density in Aligned Arrays of Single‐Walled Carbon Nanotubes by Sequential Chemical Vapor Deposition on Quartz , 2010, Advanced materials.

[18]  S. Wong,et al.  Monolithic 3D Integrated Circuits , 2007, 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

[19]  Hai Wei,et al.  Carbon Nanotube Robust Digital VLSI , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  S. Barman,et al.  Self-Sorted, Aligned Nanotube Networks for Thin-Film Transistors , 2008, Science.

[21]  Sheng Wang,et al.  Carbon nanotube based ultra-low voltage integrated circuits: Scaling down to 0.4 V , 2012 .

[22]  Xue Lin,et al.  Synthesis and device applications of high-density aligned carbon nanotubes using low-pressure chemical vapor deposition and stacked multiple transfer , 2010 .

[23]  Jianmin Miao,et al.  Growth of horizontally aligned dense carbon nanotubes from trench sidewalls , 2011, Nanotechnology.

[24]  Shekhar Y. Borkar.  3D integration for energy efficient system design , 2006, 2009 Symposium on VLSI Technology.

[25]  Mark S. Lundstrom,et al.  Sub-10 nm carbon nanotube transistor , 2011, 2011 International Electron Devices Meeting.

[26]  H.-S. Philip Wong,et al.  Digital VLSI logic technology using Carbon Nanotube FETs: Frequently Asked Questions , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[27]  H.-S. Philip Wong,et al.  First Demonstration of AC Gain From a Single-walled Carbon Nanotube Common-Source Amplifier , 2006, 2006 International Electron Devices Meeting.

[28]  Nishant Patil,et al.  Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[29]  L. Qu,et al.  Preferential syntheses of semiconducting vertically aligned single-walled carbon nanotubes for direct use in FETs. , 2008, Nano letters.

[30]  Hai Wei,et al.  Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[31]  John A Rogers,et al.  Alignment controlled growth of single-walled carbon nanotubes on quartz substrates. , 2009, Nano letters.

[32]  Hai Wei,et al.  Efficient metallic carbon nanotube removal readily scalable to wafer-level VLSI CNFET circuits , 2010, 2010 Symposium on VLSI Technology.

[33]  Hai Wei,et al.  VMR: VLSI-compatible metallic carbon nanotube removal for imperfection-immune cascaded multi-stage digital logic circuits using Carbon Nanotube FETs , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[34]  Hai Wei,et al.  Linear increases in carbon nanotube density through multiple transfer technique. , 2011, Nano letters.

[35]  Chongwu Zhou,et al.  Metal contact engineering and registration-free fabrication of complementary metal-oxide semiconductor integrated circuits using aligned carbon nanotubes. , 2011, ACS nano.

[36]  Makoto Motoyoshi,et al.  Through-Silicon Via (TSV) , 2009, Proceedings of the IEEE.

[37]  S. Lalley.  RENEWAL THEORY , 2014 .

[38]  H.-S. Philip Wong,et al.  Increasing the semiconducting fraction in ensembles of single-walled carbon nanotubes , 2012 .

[39]  Yan Li,et al.  Self-aligned ballistic n-type single-walled carbon nanotube field-effect transistors with adjustable threshold voltage. , 2008, Nano letters.

[40]  Sheng Wang,et al.  CMOS-based carbon nanotube pass-transistor logic integrated circuits , 2012, Nature Communications.

[42]  J. Mazurier,et al.  Advances, challenges and opportunities in 3D CMOS sequential integration , 2011, 2011 International Electron Devices Meeting.

[43]  J. Gilman,et al.  Nanotechnology , 2001 .

[44]  M. Lundstrom,et al.  Ballistic carbon nanotube field-effect transistors , 2003, Nature.

[45]  Hong-Yu Chen,et al.  Low-Resistance Electrical Contact to Carbon Nanotubes With Graphitic Interfacial Layer , 2012, IEEE Transactions on Electron Devices.

[46]  Nishant Patil,et al.  Carbon Nanotube circuits in the presence of carbon nanotube density variations , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[47]  Hai Wei,et al.  Scalable Carbon Nanotube Computational and Storage Circuits Immune to Metallic and Mispositioned Carbon Nanotubes , 2011, IEEE Transactions on Nanotechnology.

[48]  Hai Wei,et al.  Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[49]  H. Wong,et al.  Modeling and Analysis of Planar-Gate Electrostatic Capacitance of 1-D FET With Multiple Cylindrical Conducting Channels , 2007, IEEE Transactions on Electron Devices.

[50]  Albert Lin,et al.  Current Scaling in Aligned Carbon Nanotube Array Transistors With Local Bottom Gating , 2010, IEEE Electron Device Letters.

[51]  Hai Wei,et al.  ACCNT: A Metallic-CNT-Tolerant Design Methodology for Carbon Nanotube VLSI: Analyses and Design Guidelines , 2010, IEEE Transactions on Electron Devices.

[52]  Hai Wei,et al.  Carbon nanotube electronics - Materials, devices, circuits, design, modeling, and performance projection , 2011, 2011 International Electron Devices Meeting.

[53]  J. Rogers,et al.  Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates , 2008, Nature.

[54]  H.-S. Philip Wong,et al.  A non-iterative compact model for carbon nanotube FETs incorporating source exhaustion effects , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[55]  Davood Shahrjerdi,et al.  High device yield carbon nanotube NFETs for high-performance logic applications , 2011, 2011 International Electron Devices Meeting.

[56]  P. Avouris,et al.  Engineering Carbon Nanotubes and Nanotube Circuits Using Electrical Breakdown , 2001, Science.

[57]  H. Wong,et al.  Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes , 2009, IEEE Transactions on Nanotechnology.

[58]  Jie Zhang,et al.  Overcoming carbon nanotube variations through co-optimized technology and circuit design , 2011, 2011 International Electron Devices Meeting.