A 9-bit 500-MS/s 6.0-mW dynamic pipelined ADC using time-domain linearized dynamic amplifiers

This paper presents a dynamic pipelined analog-to-digital converter (ADC). A time-domain linearization technique is proposed to enhance the linearity of dynamic amplifiers. Also, an inverter threshold voltage based method is proposed to calibrate the common mode voltage of the dynamic amplifier. Furthermore, a capacitor digital-to-analog converter (CDAC) based method is used to calibrate the stage-gain of pipelined ADC. The prototype designed in a 65-nm CMOS technology realizes a 50.5-dB SNDR at a 500-MS/s sampling rate with a Nyquist input. It consumes 6.0-mW at a 1.2-V power supply and achieves 44 fJ per conversion step.

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