An efficient hardware accelerator architecture for implementing fast IMDCT computation

In this paper, a new fast inverse modified discrete cosine transform (IMDCT) algorithm and an efficient hardware accelerator architecture are proposed. The proposed fast algorithm is derived from our previously presented type-IV discrete cosine transform/type-IV discrete sine transform (DCT-IV/DST-IV) decomposition algorithm. After transformations of DST-IV to DCT-IV and DCT-IV to IDCT-II, the computational items are further recombined to share hardware resources. Experimental results show that the proposed algorithm's computational cycles are decreased by 20% and 51%, respectively compared with two other reported fast algorithms. By employing resource sharing and multiplexing techniques, the proposed hardware accelerator reduces 24% and 48% of transistors compared with two other ones, respectively.

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