Threshold-voltage balance for minimum supply operation

The difference between the threshold voltages (Vt) of PMOS and NMOS transistor is a critical issue in the operation of low voltage circuits. The P/N Vt balancing profit is analyzed in terms of sub-threshold leakage current, minimum supply voltage, and static noise margin. Balancing the P/N Vt reduces the lowest required supply voltage by 0.15-0.3 V. The use of our proposed Vt matching scheme enables CMOS LSI minimum supply voltage processing at 0.1 V.

[1]  G. Ono,et al.  A 1000-MIPS/W microprocessor using speed adaptive threshold-voltage CMOS with forward bias , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[2]  Masashi Horiguchi,et al.  Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's , 1993 .

[3]  Masayuki Miyazaki,et al.  Quantitative Study of an SA-Vt CMOS Circuit : Evaluation of Fluctuation in Device and Circuit Performance , 2000 .

[4]  E. Nowak,et al.  Low-power CMOS at Vdd = 4kT/q , 2001, Device Research Conference. Conference Digest (Cat. No.01TH8561).

[5]  J. Meindl,et al.  The impact of intrinsic device fluctuations on CMOS SRAM cell stability , 2001, IEEE J. Solid State Circuits.

[6]  A. R. Newton,et al.  Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .

[7]  Bomy Chen,et al.  Scalability and biasing strategy for CMOS with active well bias , 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

[8]  Tsuyoshi Shibata,et al.  Performance fluctuations of 0.10 /spl mu/m MOSFETs-limitation of 0.1 /spl mu/m ULSIs , 1994, Proceedings of 1994 VLSI Technology Symposium.

[9]  R. M. Swanson,et al.  Ion-implanted complementary MOS transistors in low-voltage circuits , 1972 .