A novel design approach of ATM switches for VLSI implementations

A novel design approach of combined input/output buffered ATM switches, is presented. The switch design problem is formulated as a non-linear discrete optimization problem: given the system requirements such as packet delay, loss probability, and switch throughput, find the input buffer size Bi, output buffer size Bo, and speed-up factor L, of a N by N such switch such that the switch implementation cost, the number of pin-limited chips, is minimized. This approach uses a simple and accurate Markov chain performance analysis which can deal with arbitrary switch size and buffer sizes. Different switch and FIFO architectures are compared from VLSI implementation aspects to show design trade-offs and necessity of the proposed design approach.<<ETX>>