Address buffer circuit of semiconductor device

1. the art that the invention defined in the claims A semiconductor memory device. 2. The invention attempts to solve the technical challenges Separating the input path of the respective address signal from address buffer circuit for inputting the two or more address signals and also controlled individually. 3. Resolution of the subject matter of the invention, An address buffer circuit of a dynamic random access memory device to perform the normal mode and the refresh mode, the input external address signal, and outputs the external address in case the start input external address signal to the first node, and blocks external address by the external address end signal a first switching device for inputting an external address enable signal for setting the input margin of the first input unit, and a refresh address input to the second input unit, and an external address and outputting a refresh address signal generated in a control signal occurs, the first node and a second switching element for inputting the refresh address enable signal for setting the input margin of the refresh address and the first switching element when the normal mode is turned on output select an external address enable signal and the refresh mode for the second switching device is turned on the refresh address enable signal And an address selection unit for selecting output, the first latch is the address of the node, and an output module configured to output an address of the address latch enable signal in case of a corresponding mode being corresponding to the set mode. 4. An important use of the invention, In the address buffer circuit in accordance with the characteristics of each mode individually control the address input speed to also implement a high-speed semiconductor memory device.