Concurrent Hw/Sw Design For Telecommunication Systems
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[1] Roberto Padovani,et al. Increased Capacity Using CDMA for Mobile Satellite Communication , 1990, IEEE J. Sel. Areas Commun..
[2] Edward A. Lee,et al. Scheduling dynamic dataflow graphs with bounded memory using the token flow model , 1993, 1993 IEEE International Conference on Acoustics, Speech, and Signal Processing.
[3] Heinrich Meyr,et al. Synchronization in digital communications , 1990 .
[4] Heinrich Meyr,et al. Dynamic data flow and control flow in high level DSP code synthesis , 1994, Proceedings of ICASSP '94. IEEE International Conference on Acoustics, Speech and Signal Processing.
[5] Rainer Leupers,et al. Methods for retargetable DSP code generation , 1994, Proceedings of 1994 IEEE Workshop on VLSI Signal Processing.
[6] C. E. SHANNON,et al. A mathematical theory of communication , 1948, MOCO.
[7] Ira Krepchin,et al. Texas Instruments Inc. , 1963, Nature.
[8] Ludwig D. J. Eggermont. VLSI signal processing, VI , 1993 .
[9] Heinrich Meyr,et al. ADEN: an environment for digital receiver ASIC design , 1995, 1995 International Conference on Acoustics, Speech, and Signal Processing.
[10] Heinrich Meyr,et al. Rapid prototyping of a DMSK transceiver , 1995, 1995 IEEE 45th Vehicular Technology Conference. Countdown to the Wireless Twenty-First Century.
[11] Klaus ten Hagen. Abstrakte Modellierung digitaler Schaltungen , 1995 .
[12] Heinrich Meyr,et al. Digital Receiver Design Using VHDL Generation From Data Flow Graphs , 1995, 32nd Design Automation Conference.
[13] Heinrich Meyr,et al. High-Level Software Synthesis for the Design of Communication Systems , 1993, IEEE J. Sel. Areas Commun..
[14] Y. Be'ery,et al. An application-specific DSP for portable applications , 1993, Proceedings of IEEE Workshop on VLSI Signal Processing.
[15] George J. Milne. Formal Specification and Verification of Digital Systems , 1994 .
[16] Heinrich Meyr,et al. Advanced digital receiver principles and technologies for PCS , 1995 .
[17] Heinrich Meyr,et al. The Differential CORDIC Algorithm: Constant Scale Factor Redundant Implementation without Correcting Iterations , 1996, IEEE Trans. Computers.
[18] K.S. Shanmugan. Simulation and implementation tools for signal processing and communication systems , 1994, IEEE Communications Magazine.
[19] S. M. Kafka. An assembly source level global compacter for digital signal processors , 1990, International Conference on Acoustics, Speech, and Signal Processing.
[20] K. W. Leary,et al. DSP/C: a standard high level language for DSP and numeric processing , 1990, International Conference on Acoustics, Speech, and Signal Processing.
[21] Anantha P. Chandrakasan,et al. Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.
[22] A.J. Viterbi,et al. Wireless digital communication: a view based on three lessons learned , 1991, IEEE Communications Magazine.
[23] J. Hindering,et al. CDMA Mobile Station Modem ASIC , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.
[24] Edward A. Lee,et al. Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing , 1989, IEEE Transactions on Computers.
[25] Stefan A. Fechtel,et al. Combined equalization, decoding and antenna diversity combining for mobile/personal digital radio transmission using feedforward synchronization , 1993, IEEE 43rd Vehicular Technology Conference.
[26] Peter Zepter,et al. Generating synchronous timed descriptions of digital receivers from dynamic data flow system level configuration , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.
[27] H. Meyr,et al. Systematic design optimization of a competitive soft-concatenated decoding system , 1993, Proceedings of IEEE Workshop on VLSI Signal Processing.
[28] E.A. Lee. Programmable DSP architectures. II , 1989, IEEE ASSP Magazine.