Efficient control state-space search

We develop algorithms for exploring the reachable state-space of hardware designs that can be partitioned into control and data. The core procedure is a symbolic algorithm that tries to visit as many controller states as is computationally feasible. Here, we describe heuristics for making this traversal efficient. Experiments demonstrate that our approach is capable of achieving significantly greater coverage of the control state-space than conventional symbolic reachability analysis.

[1]  Robert K. Brayton,et al.  Heuristic Minimization of BDDs Using Don't Cares , 1994, 31st Design Automation Conference.

[2]  Adnan Aziz,et al.  Enhancing simulation with BDDs and ATPG , 1999, DAC '99.

[3]  Sérgio Vale Aguiar Campos,et al.  Symbolic Model Checking , 1993, CAV.

[4]  Enrico Macii,et al.  A structural approach to state space decomposition for approximate reachability analysis , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[5]  F. Somenzi,et al.  High-density reachability analysis , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[6]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[7]  Tiziano Villa,et al.  VIS: A System for Verification and Synthesis , 1996, CAV.

[8]  A. Richard Newton,et al.  Implicit manipulation of equivalence classes using binary decision diagrams , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[9]  Kenneth L. McMillan,et al.  Approximation and decomposition of binary decision diagrams , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).