Numerical Error Minimizing Floating-Point to Fixed-Point ANSI C Compilation

This paper presents an ANSI C floating-point to fixed-point conversion capability currently being integrated within an application specific processor architecture/compiler co-development project at the University of Toronto. The conversion process utilizes profiling data to capture the dynamic range of floating-point variables and intermediate calculations to guide in the generation of scaling operations. An algorithm for generating shift operations resulting in a minimization of numerical error due to truncation, rounding and overflow is presented along with a novel DSP-ISA operation: fractional-multiplication with integrated left-shift. Improvements in SQNR over previous approaches of up to 6.5 dB, 3.0 dB, 7.9 dB and 12.8 dB, equivalent to 1.1, 0.5, 1.0, and 2.1 extra bits of precision carried throughout the computations are shown for, respectively, a 4th order IIR filter, 16th order lattice filter, radix-2 FFT, and a non-linear feedback control law.

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