Real time echo cancellation is an important feature for hands-free operation of telecommunication equipment like mobile phones. A desirable acoustic echo control should be capable of handling double-talk as well. In this paper, we successfully implement a novel hardware architecture that is based on a robust adaptive algorithm in combination with a two-path model to tackle the double-talk situation. The echo-canceller is working in the frequency domain and is improved by bitwidth optimization to enhance computational efficiency. In experiments, our implementation of the hardware acceleration of the echo-canceller is fast and outperforms common software implementations running on microprocessors: an implementation with 4 instances of the filter on a Xilinx XC4VFX60 FPGA running at 137MHz can run 40 times faster than software on a 3.2GHz Core 2 Duo PC. Besides, the hardware acceleration also reduces 90% of the power consumption when compared to a pure soft-core implementation. Our results suggest that the employed hardware architecture is also very energy-efficient.
[1]
Su An Jang,et al.
Design and implementation of an acoustic echo canceller
,
2002,
Proceedings. IEEE Asia-Pacific Conference on ASIC,.
[2]
B. Farhang-Boroujeny,et al.
FPGA implementation of acoustic echo cancelling
,
1999,
Proceedings of IEEE. IEEE Region 10 Conference. TENCON 99. 'Multimedia Technology for Asia-Pacific Information Infrastructure' (Cat. No.99CH37030).
[3]
Frederick R. Forst,et al.
On robust estimation of the location parameter
,
1980
.
[4]
Sven Nordholm,et al.
Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation
,
2006,
ERSA.
[5]
Jacob Benesty,et al.
An introduction to acoustic echo and noise control
,
2000
.
[6]
Sven Nordholm,et al.
New weight transform schemes for delayless subband adaptive filtering
,
2001,
GLOBECOM'01. IEEE Global Telecommunications Conference (Cat. No.01CH37270).