Automatically generating custom instruction set extensions

General-purpose processors that are utilized as cores are often incapable of achieving the challenging cost, performance, and power demands of high-performance audio, video, and networking applications. To meet these demands, most systems employ a number of hardware accelerators to off-load the computationally demanding portions of the application. As an alternative to this strategy, we examine customizing the computation capabilities of a core processor for a particular application. Our goal is to enable some or all of the computation that is off-loaded to the accelerators to be taken over by the customized core. The computation capabilities of the core processor are extended with hardware in the form of a set custom function units and new instructions. The compiler is responsible for analyzing the target application and identifying a set of cost-effective custom function units. In this paper, we provide an overview of the system that we are developing to automatically identify instruction set extensions and report some preliminary analysis of four media benchmarks.

[1]  Michael D. Smith,et al.  A high-performance microarchitecture with hardware-programmable functional units , 1994, Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture.

[2]  Ing-jer Huang,et al.  Co-Synthesis of Instruction Sets and Microarchitectures , 1994 .

[3]  Michael J. Wirthlin,et al.  DISC: the dynamic instruction set computer , 1995, Optics East.

[4]  Bruce K. Holmer Automatic Design of Computer Instruction Sets , 1993 .

[5]  Kurt Keutzer,et al.  Instruction selection using binate covering for code size optimization , 1995, ICCAD.

[6]  Chris Weaver,et al.  CryptoManiac: a fast flexible architecture for secure communication , 2001, ISCA 2001.

[7]  Trevor Mudge,et al.  MiBench: A free, commercially representative embedded benchmark suite , 2001 .

[8]  Harvey F. Silverman,et al.  Processor reconfiguration through instruction-set metamorphosis , 1993, Computer.

[9]  Edward S. Davidson,et al.  Design of instruction set architectures for support of high-level languages , 1984, ISCA 1984.

[10]  Paolo Faraboschi,et al.  Custom-fit processors: letting applications define architectures , 1996, Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29.

[11]  Werner Geurts Accelerator Data-Path Synthesis for High-Throughput Signal Processing Applications , 1996 .

[12]  Shail Aditya,et al.  Cycle-time aware architecture synthesis of custom hardware accelerators , 2002, CASES '02.

[13]  John Wawrzynek,et al.  Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[14]  Paolo Ienne,et al.  Automatic topology-based identification of instruction-set extensions for embedded processors , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[15]  J. P. Bennett A methodology for automated design of computer instruction sets , 1987 .

[16]  B. Ramakrishna Rau,et al.  Automatic Architecture Synthesis and Compiler Retargeting for VLIW and EPIC Processors , 2000 .

[17]  Rainer Leupers,et al.  Instruction selection for embedded DSPs with complex instructions , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

[18]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.