Circulating Current Analysis and the Improved D–Σ Digital Control Strategy for Multiparalleled Three-Level T-Type Grid-Connected Inverters

An improved division–summation (D–Σ) digital control strategy without high-speed communication is proposed in this paper. Unlike the traditional zero-sequence circulating current control method, the interphase circulating current suppression method is discussed and implemented on the basis of the single-phase equivalent circuit in this strategy. The generation mechanism of the interphase circulating current is emphatically analyzed. Output voltage compensation and virtual impedance compensation are studied and integrated with the D–Σ digital control method to suppress the circulating current. Experimental platform with three paralleled three-level T-type grid-connected inverters has been set up. The experiments are carried out under the conditions of the impedance match or mismatch among the inverters, the unbalanced grid voltages, and the dynamic process such as start-up and step current change. The experimental results verify that the improved D–Σ digital control strategy may effectively restrain the circulating current under various conditions.