A high-speed multiplexer-based fine-grain pipelined architecture for digital fuzzy logic controllers

Design and implementation of a high-speed multiplexer-based fine-grain pipelined architecture for a general digital fuzzy logic controller has been presented. All the operators have been designed at gate level. For the multiplication, a multiplexer-based modified Wallace tree multiplier has been designed, and for the division and addition multiplexer-based non-restoring parallel divider and multiplexer-based Manchester adder have been used, respectively. To further increase the processing speed, fine-grain pipelining technique has been employed. By using this technique, the critical path of the circuit is broken into finer pieces. Based on the proposed architecture, and by using Quartus II 9.1, a sample two-input, one-output digital fuzzy logic controller with eight rules has been successfully synthesised and implemented on Stratix II field programmable gate array. Simulations were carried out using DSP Builder in the MATLAB/Simulink tool at a maximum clock rate of 301.84 MHz.

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