A high-performance configurable VLSI architecture for integer motion estimation in H.264
暂无分享,去创建一个
[1] Liang-Gee Chen,et al. Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264 , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..
[2] Chein-Wei Jen,et al. On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture , 2002, IEEE Trans. Circuits Syst. Video Technol..
[3] Cao Wei,et al. A high-performance reconfigurable VLSI architecture for vbsme in H.264 , 2008, IEEE Transactions on Consumer Electronics.
[4] Thomas Wiegand,et al. Draft ITU-T recommendation and final draft international standard of joint video specification , 2003 .
[5] Chien-Min Ou,et al. An efficient VLSI architecture for H.264 variable block size motion estimation , 2005, IEEE Transactions on Consumer Electronics.
[6] Cao Wei,et al. A novel VLSI architecture for VBSME in MPEG-4 AVC/H.264 , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[7] Jinwook Kim,et al. A novel VLSI architecture for full-search variable block-size motion estimation , 2009, IEEE Transactions on Consumer Electronics.