The design of a charge-integrating modified floating-point ADC chip
暂无分享,去创建一个
[1] Asad A. Abidi,et al. A 10-b, 75-MHz two-stage pipelined bipolar A/D converter , 1993 .
[2] Gunther Haller,et al. Analog floating-point BiCMOS sampling chip and architecture of the BaBar CsI calorimeter front-end electronics system at the SLAC B-factory , 1996 .
[3] K. Kattmann,et al. A Technique For Reducing Differential Non-linearity Errors In Flash A/D Converters , 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[4] R. Petschacher,et al. A 10-b 75-MSPS subranging A/D converter with integrated sample and hold , 1990 .
[5] P. Pangaud,et al. Custom integrated front-end circuit for the CMS electromagnetic calorimeter , 2000, 2000 IEEE Nuclear Science Symposium. Conference Record (Cat. No.00CH37149).
[6] C. S. Chen,et al. A 20 b dynamic-range floating-point data acquisition system , 1991 .
[7] T. Zimmerman,et al. A second generation charge integrator and encoder ASIC , 1995, 1995 IEEE Nuclear Science Symposium and Medical Imaging Conference Record.