Automatic Error Correcting Hardware Implementation of AES Algorithm

We propose a fault tolerance AES hardware implementation to prevent attackers from injecting faults in the process of AES design.The design adds Hamming Code error correction circuits into the original AES implementation and it can correct all single-fault in the same byte automatically.Hardware simulation shows that the ratio of fault detection is close to 100%.The results of analyzing of different architecture and configuration of check points certificate that our proposal is very practical.