论文信息 - A simple characterization method for MOS transistor matching in deep submicron technologies

A simple characterization method for MOS transistor matching in deep submicron technologies

A new and simple four parameter mismatch model is presented for the MOS transistor. This model is extensively tested on a 0.18 /spl mu/m CMOS technology. Bulk bias dependence is modeled physically and no extra parameter is needed for long channel transistors. The repeatability of the measurement system and parameter extraction has been investigated. It is shown that for the measurement set-up and test structures, measurements in the linear region are affected by contact resistance variation for devices broader than 4 /spl mu/m.

Willy Sansen | S. Decoutere | Herman Maes | M. Rosmeulen | J. A. Croon

[1] Eric A. Vittoz. The Design of High-Performance Analog Circuits on Digital CMOS Chips , 1985 .

[2] T. Serrano-Gotarredona,et al. A new five-parameter MOS transistor mismatch model , 2000, IEEE Electron Device Letters.

[3] A.H. Montree,et al. Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistors , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[4] Gabor C. Temes,et al. Random error effects in matched MOS capacitors and current sources , 1984 .

[5] Michiel Steyaert,et al. Impact of transistor mismatch on the speed-accuracy-power trade-off of analog CMOS circuits , 1996, Proceedings of Custom Integrated Circuits Conference.

[6] K. Takeuchi,et al. Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuation , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[7] M.J.M. Pelgrom,et al. Matching properties of MOS transistors , 1989 .

[8] W. Sansen,et al. Mismatch Characterization of Submicron MOS Transistors , 1997 .

[9] K. R. Lakshmikumar,et al. Characterisation and modeling of mismatch in MOS transistors for precision analog design , 1986 .