Monolithic 3D integration: A powerful alternative to classical 2D scaling

Monolithic or sequential 3D Integration is a powerful technological enabler for actual 3D IC design as the stacked layers can be connected at the transistor scale. This paper reviews the opportunities brought by M3DI and highlights the applications benefiting from this small 3D contact pitch. It also presents the technological challenges of this concept and offers a general overview of the potential solutions to obtain a high performance low temperature top transistor while keeping bottom MOSFET integrity.

[1]  Geoffrey Yeap,et al.  Smart mobile SoCs driving the semiconductor industry: Technology trend, challenges and opportunities , 2013, 2013 IEEE International Electron Devices Meeting.

[2]  F. Clermidy,et al.  3D sequential integration opportunities and technology optimization , 2014, IEEE International Interconnect Technology Conference.

[3]  P. Batude,et al.  Setting up 3D sequential integration for back-illuminated CMOS image sensors with highly miniaturized pixels with low temperature fully depleted SOI transistors , 2008, 2008 IEEE International Electron Devices Meeting.

[4]  Gerald Cibrario,et al.  3D FPGA using high-density interconnect Monolithic Integration , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[5]  L. Napolitano.  Materials , 1984, Science.

[6]  Thomas Ernst,et al.  3-D Sequential Integration: A Key Enabling Technology for Heterogeneous Co-Integration of New Function With CMOS , 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[7]  H. Grampeix,et al.  Enabling 3D Monolithic Integration , 2008 .

[8]  Maud Vinet,et al.  FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration , 2015 .

[9]  Olivier Billoint,et al.  (Invited) Direct Bonding: A Key Enabler for 3D Monolithic Integration , 2014 .

[10]  G. Ghibaudo,et al.  Insights in accesses optimization for nFET low temperature Fully Depleted Silicon On Insulator devices , 2014, 2014 International Workshop on Junction Technology (IWJT).

[11]  J. Venturini.  Laser Thermal Annealing: Enabling ultra-low thermal budget processes for 3D junctions formation and devices , 2012, 2012 12th International Workshop on Junction Technology.

[12]  X. Garros,et al.  GeOI and SOI 3D monolithic cell integrations for high density applications , 2006, 2009 Symposium on VLSI Technology.

[13]  T. Irisawa,et al.  Demonstration of ultimate CMOS based on 3D stacked InGaAs-OI/SGOI wire channel MOSFETs with independent back gate , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.