Cache Memory Design With Magnetic Skyrmions in a Long Nanotrack

Magnetic skyrmion (MS), a vortexlike region with reversed magnetization in nanomagnets, has recently emerged as an exciting development in the field of spintronics. It has a number of beneficial features, including remarkably high stability, ultralow depinning current density, and extremely compact size. Due to these benefits, skyrmions have generated great interest in the design of spintronic memory. In this paper, we evaluate the use of skyrmion-based memory as a last-level cache for general-purpose processors. In the skyrmion-based memory structure, data can be densely packed as multiple bits in a long magnetic nanotrack. Write operations are performed by injecting a spin-polarized current in the nanotrack. Since multiple skyrmions (each representing a bit) are packed into a single nanotrack, they need to be accessed by shifting them along the nanotrack with a charge current passing through a spin-Hall metal (SHM). We identify the following key challenges associated with MS-based cache design: 1) the high-current requirements for skyrmion nucleation limit the density benefits offered by these structures, since the transistor supplying write currents is the limiting factor that determines the bit-cell area; 2) the proposed nanotrack structure results in significant performance overheads due to the latency arising from the shift operations; 3) the skyrmions move toward the edge of the nanotrack during shift operations owing to the Magnus force. Hence, an additional idle operation time is required to relax skyrmions back through the repulsive force from the edge; and 4) to avoid annihilation of skyrmions from the edge, the duration and the current density of the shift operation have to be well controlled. To overcome these challenges, a multi-bit skyrmion cell with appropriate peripheral circuit is proposed, considering the heterogeneity in the read/write characteristics. The density benefits are explored by performing the layout of different multi-bit cells. We perform a systematic device-circuit-architecture co-design to evaluate the feasibility of our proposal. Our experiments demonstrate the potential of, and the challenges involved in, using skyrmion-based memory as last-level caches.