Compact FPGA-based true and pseudo random number generators

Two FPGA-based (field programmable gate array) implementations of random number generators intended for embedded cryptographic applications are presented. The first is a true random number generator (TRNG) which employs oscillator phase noise, and the second is a bit serial implementation of a Blum Blum Shub (BBS) pseudorandom number generator (PRNG). Both designs are extremely compact and can be implemented on any FPGA of PLD device. They were designed specifically for use as FPGA-based cryptographic hardware cores. The TRNG and PRNG were tested using the NIST and Diehard random number test suites.

[1]  R. C. Fairfield,et al.  An LSI Random Number Generator (RNG) , 1985, CRYPTO.

[2]  P.H.W. Leong,et al.  Pilchard — a reconfigurable computing platform with memory slot interface , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

[3]  Peter Martin,et al.  An Analysis Of Random Number Generators For A Hardware Implementation Of Genetic Programming Using FPGAs And Handel-C , 2002, GECCO.

[4]  Elaine B. Barker,et al.  A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications , 2000 .

[5]  Mark Shand,et al.  Fast implementations of RSA cryptography , 1993, Proceedings of IEEE 11th Symposium on Computer Arithmetic.

[6]  Howard C. Card,et al.  Parallel Random Number Generation for VLSI Systems Using Cellular Automata , 1989, IEEE Trans. Computers.

[7]  S. Wolfram.  Random sequence generation by cellular automata , 1986 .

[8]  Donald Ervin Knuth,et al.  The Art of Computer Programming , 1968 .

[9]  R. Ramaswamy.  Application of a key generation and distribution algorithm for secure communication in open systems interconnection architecture , 1989, Proceedings. International Carnahan Conference on Security Technology.

[10]  Monk-Ping Leong,et al.  Pilchard - A Reconfigurable Computing Platform with Memory Slot Interface , 2001, IEEE Symposium on Field-Programmable Custom Computing Machines.

[11]  Monk-Ping Leong,et al.  Tradeoffs in Parallel and Serial Implementations of the International Data Encryption Algorithm IDEA , 2001, CHES.

[12]  염흥렬,et al.  [서평]「Applied Cryptography」 , 1997 .

[13]  Riccardo Bernardini,et al.  A fully integrated 8-bit, 20 MHz, truly random numbers generator, based on a chaotic system , 2001, 2001 Southwest Symposium on Mixed-Signal Design (Cat. No.01EX475).

[14]  Vijay V. Vazirani,et al.  Efficient and Secure Pseudo-Random Number Generation (Extended Abstract) , 1984, FOCS.

[15]  L. Kocarev,et al.  Chaos-based random number generators. Part II: practical realization , 2001 .

[16]  Christof Paar,et al.  An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[17]  Manuel Blum,et al.  A Simple Unpredictable Pseudo-Random Number Generator , 1986, SIAM J. Comput..

[18]  Alfred Menezes,et al.  Handbook of Applied Cryptography , 2018 .

[19]  Paul C. Kocher,et al.  The intel random number generator , 1999 .

[20]  Milos Drutarovský,et al.  True Random Number Generator Embedded in Reconfigurable Hardware , 2002, CHES.

[21]  Richard J. Carter,et al.  FPGA implementation of neighborhood-of-four cellular automata random number generators , 2002, FPGA '02.

[22]  Donald E. Eastlake,et al.  Randomness Recommendations for Security , 1994, RFC.

[23]  Carl Pomerance,et al.  The Development of the Number Field Sieve , 1994 .

[24]  Donald E. Knuth.  The Art of Computer Programming 2 / Seminumerical Algorithms , 1971 .

[25]  P. Alfke.  Evolution, Revolution and Convolution Recent Progress in Field-Programmable Logic , 2001 .

[26]  Vikram Pasham,et al.  High-Speed DES and Triple DES Encryptor/Decryptor , 2001 .

[27]  Donald E. Knuth,et al.  The art of computer programming, volume 3: (2nd ed.) sorting and searching , 1998 .

[28]  J. Alvin Connelly,et al.  A noise-based IC random number generator for applications in cryptography , 2000 .