A high-responsivity 9-V/Lux-s high-speed 5000-frames/s (at full 512 512 resolution) CMOS active pixel sensor (APS) is presented in this paper. The sensor was designed for a 0.35m 2P3M CMOS sensor process and utilizes a five-transistor pixel to provide a true parallel shutter. Column-parallel analog-to-digital converter (ADC) architecture yields fast readout from pixels and digitization of the data simultaneously with acquiring a new frame. The chip has a two-row SRAM to store data from the ADC and read previous rows of data out of the chip. There are a total of 16 parallel ports operating up to 90 MHz delivering 1.3 Gpixel/s or 13 Gb/s of data at the maximum rate. In conclusion, a comparison between two high-speed digital CMOS sensor architectures, which are a column-parallel APS and a digital pixel sensor (DPS), is conducted.
[1]
Hon-Sum Philip Wong,et al.
Technology and device scaling considerations for CMOS imagers
,
1996
.
[2]
Bedabrata Pain,et al.
Analysis and Enhancement of Low-Light-Level Performance of Photodiode-Type CMOS Active Pixel Images Operated with Sub-Threshold Reset
,
1999
.
[3]
B.J. Hosticka,et al.
A CMOS image sensor for high-speed imaging
,
2000,
2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).
[4]
Xinqiao Liu,et al.
A 10000 frames/s CMOS digital pixel sensor
,
2001,
IEEE J. Solid State Circuits.
[5]
Suk Hwan Lim,et al.
A 10,000 Frames/s 0.18 μm CMOS Digital Pixel Sensor with Pixel-Level Memory
,
2001
.