Methodology for modeling substrate warpage using copper trace pattern implementation

The current trend in the electronics industry is to decrease the size of electronic components while attempting to increase processing power and performance. This is leading to increased interest in thinner printed wiring boards and finer line widths and wire pitches. However, these goals can be hindered by the occurrence of warpage in the manufacturing and assembly process of electronic packages from mismatches in thermomechanical properties of the materials used. Warpage can be problematic as it leads to misalignments during package assembly, reduced tolerances, and a variety of operational failures. Current warpage prediction techniques utilize volume averaging to estimate material properties in layers of copper mixed with interlayer dielectric material. These techniques use copper percentages for an entire layer and do not account for trace orientation. This paper describes the development of a new methodology to predict the warpage of a particular substrate. The developed methodology accounts for both the trace pattern planar density and planar orientation in material property calculations for each layer of a multi-layer substrate. This process has been used to calculate the warpage of actual substrates and the results of using the developed methodology are shown to agree well with experimental data.