Built in self test: a complete test solution for telecommunication systems

The technological revolution witnessed by the telecommunications industry is leading to the development of new applications, products, and protocols, which in turn solicits widely accessible, highly reliable, and high-quality networks. To meet the stringent quality and reliability requirements of today's complex communication networks, efficient test methodologies are necessary at all levels (system, board, circuit, etc.). Conventional test methodologies are being constantly challenged by ever-increasing speed and circuit size, which results in high costs associated with test hardware, test generation, and test application time. Built-in self-test offers a test methodology where the test functions are embedded into the circuit itself. The advantages of using BIST for complex telecommunication systems are numerous. Reduced test development time, low test application time, eliminating the need for very-high-speed hardware testers, provision for at-speed tests, in-field test capability, and high fault coverage are some of them. In this article we present a tutorial on the BIST methodology targeted mainly toward telecommunication systems, the test structures necessary for its incorporation both at the circuit and system levels, and test implementation at the higher levels of design abstraction.

[1]  Parker,et al.  Design for Testability—A Survey , 1982, IEEE Transactions on Computers.

[2]  Edward McCluskey,et al.  Built-In Self-Test Techniques , 1985, IEEE Design & Test of Computers.

[3]  Vishwani D. Agrawal,et al.  A Tutorial on Built-in Self-Test. I. Principles , 1993, IEEE Des. Test Comput..

[4]  Sujit Dey,et al.  High-level synthesis for testability: a survey and perspective , 1996, DAC '96.

[5]  P. Nigh,et al.  An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[6]  Chen-Huan Chiang,et al.  BIST TPG for faults in system backplanes , 1997, ICCAD 1997.

[7]  Santanu Chattopadhyay,et al.  Additive cellular automata : theory and applications , 1997 .

[8]  Ramesh Karri,et al.  Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures , 1998, J. Electron. Test..

[9]  A. J. van de Goor,et al.  Testing Semiconductor Memories: Theory and Practice , 1998 .

[10]  Nilanjan Mukherjee,et al.  A BIST scheme for the detection of path-delay faults , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).