A hardware platform for VLIW based emulation of digital design (poster paper)

In [2] the concept of a very long instruction word (VLIW) processor based system to emulate synthesized RTlevel descriptions has been presented. As described in [2] the RAVE System(RT-Architecture-VLIW-Emulator) overcomes many of the problems common to FPGA based emulation and prototyping systems. Particularly, these are area problems in conjunction with large data paths, long turnaround times and low emulation clock frequencies. This abstract briefly describes the hardware of the RAVE System.