Scaling Down Area - Delay - Power Efficient Of Carry Select Adder Using Gdi
暂无分享,去创建一个
[1] Lee-Sup Kim,et al. 64-bit carry-select adder with reduced area , 2001 .
[2] I-Chyn Wey,et al. An Area-Efficient Carry Select Adder Design by Sharing the Common Boolean Logic Term , 2012 .
[3] S. Manju,et al. An efficient SQRT architecture of Carry Select adder design by Common Boolean logic , 2013, 2013 International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT).
[4] Orest J. Bedrij. Carry-Select Adder , 1962, IRE Trans. Electron. Comput..
[5] Chip-Hong Chang,et al. An area efficient 64-bit square root carry-select adder for low power applications , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[6] David J. Beebe,et al. VLSI in digital signal processing , 1993 .