Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs

Activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. Basic principles of partial reconfiguration are described together with the fault tolerant architectures based on the partial dynamic reconfiguration and triple modular redundancy or duplex system. Several architectures using online checkers for error detection which initiates reconfiguration process of the faulty unit are introduced as well. The modification of fault tolerant architectures into partial reconfigurable modules and main advantages of partial dynamic reconfiguration when used in fault tolerant system design are demonstrated. All presented architectures are compared with each other and proven fully functional on the ML506 development board with Virtex5 for different types of RTL digital components.

[1]  Gregory D. Peterson,et al.  Secure processing using dynamic partial reconfiguration , 2009, CSIIRW '09.

[2]  Gustavo Ribeiro Alves,et al.  On-Line Self-Healing of Circuits Implemented on Reconfigurable FPGAs , 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

[3]  John M. Emmert,et al.  A survey of fault tolerant methodologies for FPGAs , 2006, TODE.

[4]  Jürgen Teich,et al.  Platform-independent methodology for partial reconfiguration , 2004, CF '04.

[5]  John W. Lockwood,et al.  Reprogrammable network packet processing on the field programmable port extender (FPX) , 2001, FPGA '01.

[6]  Luca Sterpone,et al.  On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications , 2008, 2008 Design, Automation and Test in Europe.

[7]  Zdenek Kotásek,et al.  Digital Systems Architectures Based on On-line Checkers , 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

[8]  Luigi Carro,et al.  Designing and testing fault-tolerant techniques for SRAM-based FPGAs , 2004, CF '04.

[9]  Zdenek Kotásek,et al.  High Availability Fault Tolerant Architectures Implemented into FPGAs , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

[10]  Jürgen Becker,et al.  Tutorial on Macro Design for Dynamic and Partially Reconfigurable Systems , 2006 .

[11]  Tapan J. Chakraborty,et al.  A TMR Scheme for SEU Mitigation in Scan Flip-Flops , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).