A Cascaded Multi-level Inverter Topology with Improved Modulation Scheme

Abstract This article proposes a single-phase, cascaded multilevel inverter topology. Each of the cascaded unit cells is made up of a main inverting H-bridge leg and a level-clamping half-bridge circuit. The single-carrier, multilevel pulse-width modulation scheme is employed to generate gating signals fort he power switches. The modulation scheme is hybridized to enable the output voltage of the proposed inverter configuration, inherit the features of switching-loss reduction from fundamental pulse-width modulation, and good harmonic performance from multiple sinusoidal pulse-width modulation. A sequential switching scheme is embedded with the already employed hybrid modulation to overcome unequal switching losses among the power devices. A simple base pulse-width modulation circulation scheme is also introduced in this work to get resultant sequential switching hybrid pulse-width modulation circulation that balances power dissipation among the power modules. The proposed inverter configuration was subjected to a resistor-inductor load, and the respective numbers of output voltage level were synthesized. Fast Fourier transform (FFT) analyses of the output voltage waveforms were carried out. Analysis of the conduction power losses in the power semiconductor switches of the proposed inverter topology is given. Simulations and experiments are carried out on a 3.07-kW rated prototype of the proposed inverter for a resistor-inductor load.