The Design, Fabrication and Characterization of Independent-Gate FinFETs

[1]  A.P. Johnson,et al.  A sub 40-nm body thickness n-type FinFET , 2001, Device Research Conference. Conference Digest (Cat. No.01TH8561).

[2]  Dimitri A. Antoniadis,et al.  Back gated CMOS on SOIAS for dynamic threshold voltage control , 1995, Proceedings of International Electron Devices Meeting.

[3]  J. G. Fossum,et al.  Grasping SOI floating-body effects , 1998 .

[4]  Edward J. Nowak,et al.  High performance double-gate device technology challenges and opportunities , 2002, Proceedings International Symposium on Quality Electronic Design.

[5]  C. Sung,et al.  Single-electron transistor using self-aligned sidewall spacer gates on silicon-on-insulator nanowire , 2003, 2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003..

[6]  D. Kwong.  High-K gate dielectrics for sub-100 nm CMOS technology , 2001, Device Research Conference. Conference Digest (Cat. No.01TH8561).

[7]  E. Nowak,et al.  High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[8]  J. Treichler,et al.  Triple-self-aligned, planar double-gate MOSFETs: devices and circuits , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[9]  D. Fried,et al.  Improved independent gate N-type FinFET fabrication and characterization , 2003, IEEE Electron Device Letters.

[10]  J. Kedzierski,et al.  Demonstration of FinFET CMOS circuits , 2002, 60th DRC. Conference Digest Device Research Conference.

[11]  Charles W. Koburger,et al.  Oxidation-induced defect generation in advanced DRAM structures , 1990 .

[12]  C. Hu,et al.  Sub-50 nm P-channel FinFET , 2001 .

[13]  Kok Wai Wong,et al.  Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation , 2002, Digest. International Electron Devices Meeting,.

[14]  T. Noguchi,et al.  65 nm CMOS technology (CMOS5) with high density embedded memories for broadband microprocessor applications , 2002, Digest. International Electron Devices Meeting,.

[15]  Jong-Ho Lee,et al.  Super self-aligned double-gate (SSDG) MOSFETs utilizing oxidation rate difference and selective epitaxy , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[16]  Jerry G. Fossum,et al.  Extremely scaled fully depleted SOI CMOS , 2002, 2002 IEEE International SOI Conference.

[17]  D. Hisamoto,et al.  A fully depleted lean-channel transistor (DELTA)-a novel vertical ultrathin SOI MOSFET , 1990, IEEE Electron Device Letters.

[18]  Yuan Taur,et al.  Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs , 2001 .

[19]  Ying Zhang,et al.  Extension and source/drain design for high-performance FinFET devices , 2003 .

[20]  Robert H. Dennard,et al.  CMOS scaling for high performance and low power-the next ten years , 1995, Proc. IEEE.

[21]  H.-S.P. Wong,et al.  Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric double-gate/ground-plane CMOSFETs , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[22]  Mansun Chan,et al.  The gate misalignment effects of the sub-threshold characteristics of sub-100 nm DG-MOSFETs , 2002, Proceedings 2002 IEEE Hong Kong Electron Devices Meeting (Cat. No.02TH8616).

[23]  M. Masahara,et al.  Ideal rectangular cross-section Si-Fin channel double-gate MOSFETs fabricated using orientation-dependent wet etching , 2003, IEEE Electron Device Letters.

[24]  J. Kedzierski,et al.  A functional FinFET-DGCMOS SRAM cell , 2002, Digest. International Electron Devices Meeting,.

[25]  J. Kedzierski,et al.  A Fin-type independent-double-gate NFET , 2003, 61st Device Research Conference. Conference Digest (Cat. No.03TH8663).

[26]  C. Hu,et al.  FinFET-a self-aligned double-gate MOSFET scalable to 20 nm , 2000 .

[27]  J. Benedict,et al.  Two gates are better than one [double-gate MOSFET process] , 2003, IEEE Circuits and Devices Magazine.

[28]  L. Selmi,et al.  An experimental study of mobility enhancement in ultrathin SOI transistors operated in double-gate mode , 2003 .

[29]  D. Fried,et al.  High-performance p-type independent-gate FinFETs , 2004, IEEE Electron Device Letters.

[30]  Thomas Skotnicki,et al.  Metal gate and high-k integration for advanced CMOS devices , 2003, 2003 8th International Symposium Plasma- and Process-Induced Damage..