Portable Techniques to Find Effective Memory Hierarchy Parameters

Application performance on modern microprocessors depends heavily on performance related characteristi cs of the underlying architecture. To achieve the best performance, an application must be tuned to both the target-processor fami ly and, in many cases, to the specific model, as memory-hierarch y parameters vary in important ways between models. Manual tuning is too inefficient to be practical; we need compilers t hat perform model-specific tuning automatically. To make such tuning practical, we need techniques that can automatically discern the critical performance parameters of a new computer system. While some of these parameters can be found in manuals, many of them cannot. To further complicate matters, compiler-based optimization should t arget the system’s behavior rather than its hardware limits. Effective cache capacities, in particular, can be smaller than the har dware limits for a number of reasons, such as sharing between cores or between instruction and data caches. Physical address mapp ing can also reduce the effective cache capacity. To address these challenges, we have developed a suite of portable tools that derive many of the effective parametersof the memory hierarchy. Our work builds on a long line of prior art that uses micro-benchmarks to analyze the memory system . We separate the design of a reference string that elicits a sp ecific behavior from the analysis that interprets that behavior. We present a novel set of reference strings and a new robust appr oach to analyzing the results. We present experimental validati on on a collection of 20 processors.