An inverter chain with parallel output nodes for eliminating single-event transient pulse

The current paper presents an inverter chain with parallel output nodes design for the purpose of eliminating the single-event transient (SET) pulse. The structure of parallel output nodes combined with the layout utilizing isolation approach can eliminate the SET pulse substantially. As compared with the conventional inverter chain as well as the inverter chain of source-isolation approach and the duplicated inverter chains with C-element, the simulation results illustrate that the proposed inverter chain manifests an effective improvement of immunity to SET. With regard to P-hit, the proposed inverter chain is capable of attaining a stable output irrespective of the state of the struck PMOS being OFF or ON. With regard to N-hit, the proposed inverter chain can also maintain the final output steadily. As long as the SET pulse is not generated at the eventual output node, the pulse can be eliminated by the proposed inverter chain. Besides that, the proposed approach is also applicable to the circuits with the structure like inverter chain.

[1]  Yong-Bin Kim,et al.  Analysis and Design of Nanoscale CMOS Storage Elements for Single-Event Hardening With Multiple-Node Upset , 2012, IEEE Transactions on Device and Materials Reliability.

[2]  M. Baze,et al.  A digital CMOS design technique for SEU hardening , 2000 .

[3]  Shuming Chen,et al.  Simulation Study of the Layout Technique for P-hit Single-Event Transient Mitigation via the Source Isolation , 2012, IEEE Transactions on Device and Materials Reliability.

[4]  B.L. Bhuva,et al.  RHBD techniques for mitigating effects of single-event hits using guard-gates , 2005, IEEE Transactions on Nuclear Science.

[5]  P. Marshall,et al.  32 and 45 nm Radiation-Hardened-by-Design (RHBD) SOI Latches , 2011, IEEE Transactions on Nuclear Science.

[6]  Ziyang Chen,et al.  A radiation harden enhanced Quatro (RHEQ) SRAM cell , 2017, IEICE Electron. Express.

[7]  Ivan R. Linscott,et al.  LEAP: Layout Design through Error-Aware Transistor Positioning for soft-error resilient sequential cell design , 2010, 2010 IEEE International Reliability Physics Symposium.

[8]  R. Baumann.  Soft errors in advanced semiconductor devices-part I: the three radiation sources , 2001 .

[9]  B. L. Bhuva,et al.  Double-pulse-single-event transients in combinational logic , 2011, 2011 International Reliability Physics Symposium.

[10]  Lloyd W. Massengill,et al.  Basic mechanisms and modeling of single-event upset in digital microelectronics , 2003 .

[11]  K. Avery,et al.  Heavy ion-induced digital single-event transients in deep submicron Processes , 2004, IEEE Transactions on Nuclear Science.

[12]  M.J. Gadlage,et al.  Comparison of heavy ion and proton induced combinatorial and sequential logic error rates in a deep submicron process , 2005, IEEE Transactions on Nuclear Science.

[13]  Shuming Chen,et al.  Novel Layout Technique for Single-Event Transient Mitigation Using Dummy Transistor , 2013, IEEE Transactions on Device and Materials Reliability.

[14]  L. W. Massengill,et al.  Effect of Multiple-Transistor Charge Collection on Single-Event Transient Pulse Widths , 2011, IEEE Transactions on Device and Materials Reliability.

[15]  Qiang Zhao,et al.  A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination , 2018, IEICE Electron. Express.