A flexible LDPC decoder architecture supporting two decoding algorithms

In this paper a programmable and area-efficient decoder architecture supporting two main stream decoding algorithms for any Block-LDPC codes is presented. The novel decoder can be configured to decode in either TPMP or TDMP decoding mode according to different Block-LDPC codes. To verify our proposed architecture, a flexible LDPC decoder which supports IEEE 802.16e is implemented using a 0.13um CMOS process with a total area of 6.3 mm2 and maximum clock frequency of 260 MHz. The estimated comsumption is 270 mW when operates at 125 MHz and 1.2V supply.

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