An Optimized Implementation of Phase Locked Loops for Grid Applications

This paper presents an optimized digital implementation of phase locked loops (PLLs) for grid applications suitable for implementation in low-cost industrial devices. A robust PLL is crucial in most of power converter applications, particularly in distorted environments. That is, the phase estimation should not be affected by power quality phenomena, given by Standard EN 50160, such as harmonics, imbalance, line notching, and voltage sags. The PLL dynamics is optimized as follows. A notch filter inside the loop is implemented to enhance the steady-state filtering. The bandwidth is maximized to get a fast postfault retracking (transient response). As justified in this paper, this approach is very suitable for both single- and three-phase PLLs. A low-resource-consuming implementation of the digitally controlled oscillator is provided: A digital model based on an RC electronic oscillator implements the needed trigonometric functions. This reduces the needed digital resources without reducing the performance. The proposed PLLs have been implemented and tested in a fixed-point DSP TI TMS320LF2407. These PLLs have been tested using different distorted inputs. Experimental results show that fast and rippleless phase estimations are achieved by the proposed implementations.

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