An Energy-efficient Multi-bit Quaternary Current-mode Signaling for On-chip Interconnects
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[1] Peter Caputa,et al. An on-chip delay- and skew-insensitive multicycle communication scheme , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.
[2] B. Nauta,et al. A 3Gb/s/ch transceiver for RC-limited on-chip interconnects , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
[3] Eisse Mensink,et al. A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip interconnects , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[4] K.L. Shepard,et al. Distributed Loss Compensation for Low-latency On-chip Interconnects , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.
[5] Uri C. Weiser,et al. Interconnect-power dissipation in a microprocessor , 2004, SLIP '04.
[6] Krishna C. Saraswat,et al. Scaling trends for the on chip power dissipation , 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).
[7] Jian Xu,et al. A 32Gb/s On-chip Bus with Driver Pre-emphasis Signaling , 2006, IEEE Custom Integrated Circuits Conference 2006.
[8] K. W. Current. Current-mode CMOS multiple-valued logic circuits , 1994 .
[9] A. Jose,et al. Near speed-of-light on-chip interconnects using pulsed current-mode signalling , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..
[10] Ken Mai,et al. The future of wires , 2001, Proc. IEEE.