ET 2 : a metric for time and energy efficiency of computation

We investigate an efficiency metric for VLSI computation that includes energy. E, and time, t, in the form Et2. We apply the metric to CMOS circuits operating outside velocity saturation when energy and delay can be exchanged by adjusting the supply voltage; we prove that under these assumptions, optimal Et2 implies optimal energy and delay. We give experimental and simulation evidences of the range and limits of the assumptions. We derive several results about sequential, parallel, and pipelined computations optimized for Et2, including a result about the optimal length of a pipeline.We discuss transistor sizing for optimal Et2 and show that, for fixed, nonzero execution rates, the optimum is achieved when the sum of the transistor-gate capacitances is twice the sum of the parasitic capacitances--not for minimum transistor sizes. We derive an approximation for Etn (for arbitrary n) of an optimally sized system that can be computed without actually sizing the transistors; we show that this approximation is accurate. We prove that when multiple, adjustable supply voltages are allowed, the optimal Et2 for the sequential composition of components is achieved when the supply voltages are adjusted so that the components consume equal power. Finally, we give rules for computing the Et2 of the sequential and parallel compositions of systems, when the Et2 of the components are known.