Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving
暂无分享,去创建一个
[1] Michael S. Hsiao,et al. Design validation of RTL circuits using evolutionary swarm intelligence , 2012, 2012 IEEE International Test Conference.
[2] Fabio Somenzi,et al. Guiding simulation with increasingly refined abstract traces , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[3] Alan J. Hu,et al. An Effective Guidance Strategy for Abstraction-Guided Simulation , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[4] Per Bjesse,et al. Using counter example guided abstraction refinement to find complex bugs , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[5] Tao Zhang,et al. An abstraction-guided simulation approach using Markov models for microprocessor verification , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[6] Lingyi Liu,et al. STAR: Generating input vectors for design validation by static analysis of RTL , 2009, 2009 IEEE International High Level Design Validation and Test Workshop.
[7] Jian Wang,et al. Functional test generation guided by steady-state probabilities of abstract design , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[8] Michael S. Hsiao,et al. Sequential circuit test generation using dynamic state traversal , 1997, Proceedings European Design and Test Conference. ED & TC 97.
[9] Xiaowei Li,et al. Observability Statement Coverage Based on Dynamic Factored Use-Definition Chains for Functional Verification , 2006, J. Electron. Test..
[10] W. Marsden. I and J , 2012 .
[11] Michael S. Hsiao,et al. Efficient Design Validation Based on Cultural Algorithms , 2008, 2008 Design, Automation and Test in Europe.
[12] Shobha Vasudevan,et al. Efficient validation input generation in RTL by hybridized source code analysis , 2011, 2011 Design, Automation & Test in Europe.
[13] Alan J. Hu. Distance-Guided Hybrid Verification with GUIDO , 2006, 2006 IEEE International High Level Design Validation and Test Workshop.
[14] Tao Lv,et al. An Observability Branch Coverage Metric Based on Dynamic Factored Use-Define Chains , 2006, 2006 15th Asian Test Symposium.
[15] Xiaowei Li,et al. Path Constraint Solving Based Test Generation for Hard-to-Reach States , 2013, 2013 22nd Asian Test Symposium.
[16] Frank van Harmelen,et al. Handbook of Knowledge Representation , 2008, Handbook of Knowledge Representation.
[17] R. Kalyanaraman,et al. Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming , 1995, IEEE Trans. Very Large Scale Integr. Syst..
[18] Koushik Sen,et al. DART: directed automated random testing , 2005, PLDI '05.
[19] V. Kamakoti,et al. Automatic Constraint Based Test Generation for Behavioral HDL Models , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.