Efficient VLSI architecture for 2-D inverse discrete wavelet transforms

In this paper, we present a high-performance VLSI architecture for 2-D inverse discrete wavelet transforms (IDWT). The architecture is designed based on a computation-schedule scheme to process the input signals in real-time, and uses two efficient filter structures to minimize the hardware cost. For the computation of an N/spl times/N 2-D image with a filter length L, this architecture spends nearly N/sup 2/ clock cycles, and requires about NL storage unit, 3 1/2 L multipliers, as well as 7(L/2-1)+4 adders.