Hybrid wave-pipelined adder

In arithmetic circuits low latency and high throughput are desirable. These performance Constraints are not expected in conventional systems. Pipeline is introduced in arithmetic circuits to enhance the above performance constraints to get the desired throughput in pipelined systems with the penalty of area and power Consumption. This can be alleviated in hybrid model of pipeline and wave pipeline is known as hybrid wave Pipeline. On the other hand wave pipelined Circuits; Path delay equalization and clock period minimization are Critical. In this paper we present a FPGA Implementation of hybrid wave pipelined adder operates at 500 MHz, performance improvement compared to conventional pipelined and wave pipelined adder. Clock frequency is minimized and delays with clock skew are compromised in proposed adder.