An exhaustive experimantal study of the high frequency noise properties of MOSFET in Silicon--on--Insulator (SOI) technology is presented. Various gate geometries are fabricated to study the influence of effective channel lenght and gate finger width on the four noise parameters. The high level of MOSFET sensitivity to the monimum noise matching condition is demonstranted. From experimental results, optimization ways to realize ultra low noise amplifiers are discussed. The capability of the fully depleted standard SOI CMos process for realizing low noise amplifiers for multigigahertz portable communication systems is shown. A monimum noise figure of about 0.7 dB and an available gain of 15 dB at 2 GHz have been obtained in the case of 0.6 um effective gate length MOSFET. Such a performance is very promising for lower gate length processes for applications in upper frequency range.