Protocol-Aware ATE enables cooperative test between DUT and ATE for improved TTM and test quality

Coverage gaps in structural test for 65 nm can be filled with functional test that is however hindered by non-deterministic device behavior and limited access into complex autonomous SoCs. Protocol-aware ATE can tolerate non-deterministic device responses and interact intelligently with the device (CPU and DFT) through a host interface. This enables an efficient cooperative test between DUT and ATE, leveraging comprehensive access of an on-chip CPU, and the SW to do so from design verification. Such cooperative test is highly portable (TTM), realistic (test quality), and fast (cost of test). In case the SoC or SiP lacks memory for the on-chip CPU, ATE could emulate missing memories to enable a functional operation of the CPU. However, roundtrip times between DUT and ATE imply long latencies that make test less realistic and must be accommodated for by DFT in the memory controller.