Analog-digital and digital-analog converters using single-electron and MOS transistors

This paper proposes two kinds of novel single-electron analog-digital conversion (ADC) and digital-analog conversion (DAC) circuits that consist of single-electron transistors (SETs) and metal-oxide-semiconductor (MOS) transistors. The SET/MOS hybrid ADC and DAC circuits possess the merits of the SET circuit and the MOS circuit. We obtain the SPICE macro-modeling code of the SET transistor by studying and fitting the characteristics of the SET with SPICE simulation and Monte Carlo simulation methods. The SPICE macro-modeling code is used for the simulation of the SET/MOS hybrid ADC and DAC circuits. We simulate the performances of the SET/MOS hybrid 3-b ADC and 2-b DAC circuits by using the H-SPICE simulator. The simulation results demonstrate that the hybrid circuits can perform analog-digital and digital-analog data conversion well at room temperature. The hybrid ADC and DAC circuits have advantages as follows: 1) compared with conventional circuits, the architectures of the circuits are simpler; 2) compared with single electron transistor circuits, the circuits have much larger load capability; 3) the power dissipation of the circuits are lower than /spl omega/W; 4) the data conversion rate of the circuits can exceed 100 MHz; and 5) the resolution of the ADC and DAC circuits can be increased by the pipeline architectures.

[1]  Yoshihito Amemiya,et al.  Cellular-Automaton Circuits Using Single-Electron-Tunneling Junctions , 1997 .

[2]  Ultra-small physical random number generators based on Si nanodevices for security systems and comparison to other large physical random number generators , 2003, 2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003..

[3]  A.M. Ionescu,et al.  A quasi-analytical SET model for few electron circuit simulation , 2002, IEEE Electron Device Letters.

[4]  Yoshinao Mizugaki,et al.  Single-Electron Signal Modulator Designed for a Flash Analog-to-Digital Converter : Instrumentation, Measurement, and Fabrication Technology , 2001 .

[5]  Stamatis Vassiliadis,et al.  Digital to analog conversion performed in single electron technology , 2001, Proceedings of the 2001 1st IEEE Conference on Nanotechnology. IEEE-NANO 2001 (Cat. No.01EX516).

[6]  K. Banerjee,et al.  SETMOS: a novel true hybrid SET-CMOS high current Coulomb blockade oscillation cell for future nano-scale analog ICs , 2003, IEEE International Electron Devices Meeting 2003.

[7]  Siegfried Selberherr,et al.  SIMON-A simulator for single-electron tunnel devices and circuits , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Chaohong Hu,et al.  A single-electron-transistor-based analog/digital converter , 2002, Proceedings of the 2nd IEEE Conference on Nanotechnology.

[9]  Su Jin Ahn,et al.  Asynchronous analogue-to-digital converter for single-electron circuits , 1998 .

[10]  H. Inokawa,et al.  A multiple-valued logic with merged single-electron and MOS transistors , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[11]  A. Arbel,et al.  Fast ADC , 1975, IEEE Transactions on Nuclear Science.

[12]  Yun Seop Yu,et al.  Macromodeling of single-electron transistors for efficient circuit simulation , 1999 .

[13]  Fumiyuki Adachi,et al.  Low-Power Consuming Analog-Type Matched Filter for DS-CDMA Mobile Radio (Special Section on Spread Spectrum Techniques and Applications) , 1996 .

[14]  Jianfei Jiang,et al.  Analog-to-digital converter based on single-electron tunneling transistors , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  J. Y. Le,et al.  Design of hybrid SET-CMOS D/A converter , 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).

[16]  P. Hadley,et al.  Simulating Hybrid Circuits of Single-Electron Transistors and Field-Effect Transistors , 2003 .

[17]  K. Matsuzawa,et al.  Analytical Single-Electron Transistor(SET)Model for Design and Analysis of Realistic SET Circuits , 2000 .

[18]  V. Pott,et al.  Hybrid SETMOS architecture with Coulomb blockade oscillations and high current drive , 2004, IEEE Electron Device Letters.