A unique hardening technique is described which addresses SEE (Single Event Effect) problems which result in data loss in deep submicron microcircuits in space radiation environments. This hardening technique, termed the "temporally redundant sampling latch", addresses both conventional static SEUs (Single Event Upsets) and SET (Single Event Transient) induced errors. The temporal latch approach provides immunity to each of these SEE related circuit upsets with a minimal impact on microcircuit design methods, physical layout area, and circuit performance. For FPGA (Field Programmable Gate Array) designs in particular, the layout area penalty and the circuit operation speed are impacted by only a few percent. The temporally redundant latch approach therefore permits FPGAs and other microcircuits with deep submicron feature sizes to be used in space environments. It not only eliminates single event upsets, but also prevents single event transients, generated within combinatorial logic or within EEPROM (Electrically Erasable Programmable Read-Only Memory) configuration bit storage elements, from disrupting the circuit operation.
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