Impact of strain on the performance of high-k/metal replacement gate MOSFETs

This paper presents a simulation study of the impact of strain on scaled high performance pMOSFETs. The gate-last strain enhancement technique is employed in high-k/metal gate technology to fortify strain, and the underlying strain enhancement mechanism is studied. The strain contribution to performance improvement is differentiated from that due to the other beneficial aspects of the metal gate. Finally, the factors affecting device performance enhancement due to the scaling process are explored.

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