Incorporating Bottom-Up Approach Into Device/Circuit Co-Design for SRAM-Based Cache Memory Applications

In this article, a reliable static random access memory (SRAM) circuit design is proposed for improved thermal and electrical performance at 5-nm technology nodes. The proposed SRAM circuit is developed by incorporating bottom-up approach (from device level to circuit level). The proposed device/circuit design utilizes high thermal conductivity and high permittivity of titanium dioxide (TiO2). Specifically, TiO2-based vertically stacked nanosheet field-effect transistor (NSFET) in the proposed SRAM shows the improvement of maximum lattice temperature (<inline-formula> <tex-math notation="LaTeX">${T}_{\text {MAX}}$ </tex-math></inline-formula>) from 564 to 431 K, which enables the improvement of electron mobility (<inline-formula> <tex-math notation="LaTeX">$\mu _{\text {electron}}$ </tex-math></inline-formula>) by 53.1%. In addition, the proposed device structure shows the improvement of ON-current (<inline-formula> <tex-math notation="LaTeX">${I}_{\text {on}}$ </tex-math></inline-formula>)/gate current (<inline-formula> <tex-math notation="LaTeX">${I}_{\text {gate}}$ </tex-math></inline-formula>), by 18%/1000%, compared to hafnium oxide (HfO2)-based vertically stacked NSFET. Because of this thermal/electrical performance boosting, the proposed SRAM circuit shows the enhancement of hold-signal-to-noise margin SNM (HSNM), read-SNM (RSNM), read access time (RAT), and write access time (WAT) at the same time. This thermal and electrical co-improvement indicates that the proposed device structure could enable reliable IC chip design.

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