AC Power Supply Noise Simulation of CMOS Microprocessor with LSI Chip-Package-Board Integrated Model

[1]  Kouji Ichikawa,et al.  Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits , 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[2]  M. Nagata,et al.  Co-simulation of AC power noise of CMOS microprocessor using capacitor charging modeling , 2012, 2012 2nd IEEE CPMT Symposium Japan.

[3]  M. Nagata,et al.  Co-evaluation of power supply noise of CMOS microprocessor using on-board magnetic probing and on-chip waveform capturing techniques , 2012, 2012 IEEE International Meeting for Future of Electron Devices, Kansai.

[4]  Richard Perdriau,et al.  ICEM modelling of microcontroller current activity , 2004, Microelectron. J..

[5]  R. Perdriau,et al.  EMC Assessment at Chip and PCB Level: Use of the ICEM Model for Jitter Analysis in an Integrated PLL , 2007, IEEE Transactions on Electromagnetic Compatibility.

[6]  C. Lochot,et al.  ICEM: a new standard for EMC of IC definition and examples , 2003, 2003 IEEE Symposium on Electromagnetic Compatibility. Symposium Record (Cat. No.03CH37446).

[7]  Resve A. Saleh,et al.  Clock skew verification in the presence of IR-drop in the powerdistribution network , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Makoto Nagata,et al.  Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits , 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[9]  Makoto Nagata,et al.  Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.