A New Assist Technique to Enhance the Read and Write Margins of Low Voltage SRAM Cell

Improving the Noise margin is one of the important challenge in every state of the art SRAM design. Due to the Process variations like threshold voltage variations, supply voltage variations etc.. in scaled technologies, stable operation of the bit cell is critical to obtain with high yield in low-voltage SRAM. In this paper a new assist technique (Read assist and write assist) is proposed to enhance the read and write margins of the 6T SRAM bit cell and the same write assist circuit is applicable to enhance the write margin of the 8T SRAM bit cell. The simulations are performed in 90nm TSMC process Technology node and the read and write margin simulation results are compared with different SRAM circuits like 6T SRAM bit cell with cell ratio of 1, 2, 3 and Dynamic word line swing technique and 8T SRAM bit cell. The effect of temperature and threshold voltage values on Read and Write margins are observed. By using the proposed read assist technique the read margin is improved by 2.375 times for 6T cell and with write assist technique the write margin is improved by 1.89 times for 6T and 8T cells.

[1]  Anna W. Topol,et al.  Stable SRAM cell design for the 32 nm node and beyond , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[2]  A.P. Chandrakasan,et al.  Static noise margin variation for sub-threshold SRAM in 65-nm CMOS , 2006, IEEE Journal of Solid-State Circuits.

[3]  Volkan Kursun,et al.  Dynamic wordline voltage swing for low leakage and stable static memory banks , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[4]  Masahiko Yoshimoto,et al.  A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

[5]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[6]  Jiajing Wang,et al.  Analyzing static and dynamic write margin for nanometer SRAMs , 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

[7]  Zhiyu Liu,et al.  Characterization of a Novel Nine-Transistor SRAM Cell , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  M. Nomura,et al.  Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[9]  Atsushi Kawasumi,et al.  A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-ß-ratio Memory Cell , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[10]  Masahiko Yoshimoto,et al.  Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Birla Shilpi,et al.  Characterization of PNN Stack SRAM Cell at Deep Sub-Micron Technology with High Stability and Low Leakage for Multimedia Applications , 2011 .

[12]  Kaushik Roy,et al.  Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[13]  Manisha Pattanaik,et al.  Stability and Leakage Analysis of a Novel PP Based 9T SRAM Cell Using N Curve at Deep Submicron Technology for Multimedia Applications , 2011, Circuits Syst..